Hi Andy, andriy.shevchenko@xxxxxxxxxxxxxxx wrote on Tue, 12 Apr 2022 14:06:30 +0300: > On Tue, Apr 12, 2022 at 12:21:34PM +0200, Miquel Raynal wrote: > > The Renesas RZN1 DMA IP is based on a DW core, with eg. an additional > > dmamux register located in the system control area which can take up to > > 32 requests (16 per DMA controller). Each DMA channel can be wired to > > two different peripherals. > > > > We need two additional information from the 'dmas' property: the channel > > (bit in the dmamux register) that must be accessed and the value of the > > mux for this channel. > > ... > > Some headers are absent, e.g.: types.h, bitops.h. > > > +#include <linux/of_device.h> > > +#include <linux/of_dma.h> > > +#include <linux/slab.h> > > ... > > > + mutex_lock(&dmamux->lock); > > + clear_bit(BIT(map->req_idx), dmamux->used_chans); > > Why do you need atomic bit operation here _and_ mutex? > > > + mutex_unlock(&dmamux->lock); > > Ditto for the rest similar cases. We no longer need the lock however I re-ordered things like they were before because I need to add a check on the bitmap when setting the bit and this must be done before touching the dmamux registers. Thanks, Miquèl
