On Mon, 28 Mar 2022 07:49:30 +0100, Biju Das wrote: > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It > can operate in DSI mode, with up to four data lanes. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > --- > v1->v2: > * Added full path for dsi-controller.yaml > * Modeled DSI + D-PHY as single block and updated reg property > * Fixed typo D_PHY->D-PHY > * Updated description > * Added interrupts and interrupt-names and updated the example > RFC->v1: > * Added a ref to dsi-controller.yaml. > RFC:- > * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das.jz@xxxxxxxxxxxxxx/ > --- > .../bindings/display/bridge/renesas,dsi.yaml | 175 ++++++++++++++++++ > 1 file changed, 175 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
