Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC. Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Reviewed-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> --- .../bindings/clock/renesas,rzg2l-cpg.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index bd3af8fc616b..b1145f9139d2 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -4,14 +4,15 @@ $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"; $schema: "http://devicetree.org/meta-schemas/core.yaml#"; -title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode +title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode maintainers: - Geert Uytterhoeven <geert+renesas@xxxxxxxxx> description: | On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module - Standby Mode share the same register block. + Standby Mode share the same register block. On RZ/V2M, the functionality is + similar, but does not have Clock Monitor Registers. They provide the following functionalities: - The CPG block generates various core clocks, @@ -25,6 +26,7 @@ properties: enum: - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a09g011-cpg # RZ/V2M reg: maxItems: 1 @@ -42,9 +44,10 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - <dt-bindings/clock/r9a07g*-cpg.h> + <dt-bindings/clock/r9a07g*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h> - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>. + a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or + <dt-bindings/clock/r9a09g011-cpg.h>. const: 2 '#power-domain-cells': @@ -58,7 +61,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the <dt-bindings/clock/r9a07g0*-cpg.h>. + the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>. const: 1 required: -- 2.32.0
