Sort the pinctrl nodes alphabetically.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
v1->v2:
* Fixed typo in commit message
---
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 24 +++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 5f5ec21e655c..53759c3ddecb 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -12,11 +12,6 @@
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
- scif0_pins: scif0 {
- pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
- <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
- };
-
#if SW_SCIF_CAN
/* SW8 should be at position 2->1 */
can1_pins: can1 {
@@ -25,13 +20,6 @@
};
#endif
- scif1_pins: scif1 {
- pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
- <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
- <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
- <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
- };
-
#if SW_RSPI_CAN
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb-hog {
@@ -47,6 +35,18 @@
};
#endif
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
+ };
+
+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
+ <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
+ <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
+ };
+
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
--
2.17.1
