Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3] clk: renesas: rzg2l-cpg: Add support for RZ/V2L
> SoC
>
> Hi Biju,
>
> On Thu, Feb 3, 2022 at 5:51 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > The clock structure for RZ/V2L is almost identical to RZ/G2L SoC. The
> > only difference being RZ/V2L has additional registers to control the
> > clock and reset for the DRP-AI block.
> >
> > This patch reuses r9a07g044-cpg.c, as the common clock IDS are the
> > same between RZ/G2L and RZ/V2L and adding a separate
> > r9a07g054_cpg_info to take care of DRP-AI clocks.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > ---
> > v2->v3:
> > * reuse r9a07g044-cpg.c for RZ/V2L
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > @@ -11,12 +11,13 @@
> > #include <linux/kernel.h>
> >
> > #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +#include <dt-bindings/clock/r9a07g054-cpg.h>
> >
> > #include "rzg2l-cpg.h"
> >
> > enum clk_ids {
> > /* Core Clock Outputs exported to DT */
> > - LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
> > + LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,
> >
> > /* External Input Clocks */
> > CLK_EXTAL,
> > @@ -149,131 +150,142 @@ static const struct cpg_core_clk
> r9a07g044_core_clks[] __initconst = {
> > CLK_DIVIDER_HIWORD_MASK), };
> >
> > -static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
>
> [...]
>
> > +static const struct {
> > + struct rzg2l_mod_clk common[62]; #ifdef CONFIG_CLK_R9A07G054
> > + struct rzg2l_mod_clk drp[0];
> > +#endif
> > +} mod_clks = {
>
> [...]
>
> > + },
> > +#ifdef CONFIG_CLK_R9A07G054
> > + .drp = {
> > + },
> > +#endif
> > };
>
> You should do the common/drp split for core clocks and resets, too.
> It doesn't matter that much now, as currently no drp clocks or resets are
> handled yet, but doing it now avoids confusion, and makes it clear what is
> the future plan.
Agreed. Will do this changes in the next version.
Regards,
Biju
>
> > @@ -346,11 +358,34 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
> > .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
> >
> > /* Module Clocks */
> > - .mod_clks = r9a07g044_mod_clks,
> > - .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
> > + .mod_clks = mod_clks.common,
> > + .num_mod_clks = ARRAY_SIZE(mod_clks.common),
> > .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
> >
> > /* Resets */
> > .resets = r9a07g044_resets,
> > .num_resets = ARRAY_SIZE(r9a07g044_resets), };
> > +
> > +#ifdef CONFIG_CLK_R9A07G054
> > +const struct rzg2l_cpg_info r9a07g054_cpg_info = {
> > + /* Core Clocks */
> > + .core_clks = r9a07g044_core_clks,
> > + .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
> > + .last_dt_core_clk = LAST_DT_CORE_CLK,
> > + .num_total_core_clks = MOD_CLK_BASE,
> > +
> > + /* Critical Module Clocks */
> > + .crit_mod_clks = r9a07g044_crit_mod_clks,
> > + .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
> > +
> > + /* Module Clocks */
> > + .mod_clks = mod_clks.common,
> > + .num_mod_clks = ARRAY_SIZE(mod_clks.common) +
> ARRAY_SIZE(mod_clks.drp),
> > + .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
> > +
> > + /* Resets */
> > + .resets = r9a07g044_resets,
> > + .num_resets = ARRAY_SIZE(r9a07g044_resets), }; #endif
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
