On Fri, Nov 12, 2021 at 9:10 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU
> frequency. Define CPG_PL1_DDIV, so that we can register it as a
> clock divider in later patch.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
