Hi Andy, Thank you for the review. On Thu, Nov 11, 2021 at 8:52 PM Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote: > > On Thu, Nov 11, 2021 at 12:59 AM Lad Prabhakar > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > > > > Number of GPIO IRQ's supported by the chip is not always > > supported GPIO IRQs by the chip > will update the change log. > > equal to the number of GPIO pins. For example on Renesas RZ/G2L > > SoC where it has GPIO0-122 pins but at a give point a maximum > > of only 32 GPIO pins can be used as IRQ lines in the IRQC domain. > > > > This patch adds ngirq member to struct gpio_irq_chip and passes > > this as a size to irq_domain_create_hierarchy()/irq_domain_create_simple() > > if it is being set in the driver otherwise fallbacks to using ngpio. > > ... > > > gc->irq.domain = irq_domain_create_hierarchy( > > gc->irq.parent_domain, > > 0, > > - gc->ngpio, > > + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio, > > You may use ?: instead as it's done somewhere else in this module. > Agreed will do. > > gc->irq.fwnode, > > &gc->irq.child_irq_domain_ops, > > gc); > > ... > > > gc->irq.domain = irq_domain_create_simple(fwnode, > > - gc->ngpio, > > + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio, > > Ditto. > > > gc->irq.first, > > gc->irq.domain_ops ?: &gpiochip_domain_ops, > > (^^^ You see?) > Thanks for the pointer. > > gc); > > ... > > > + /** > > + * @ngirq: > > + * > > + * The number of GPIO IRQ's handled by this IRQ domain; usually is > > handled GPIO IRQs > OK, will update the description as mentioned above. > > + * equal to ngpio > > Missed period. > Ouch. Cheers, Prabhakar > > + */ > > -- > With Best Regards, > Andy Shevchenko
