Hi Biju, On Thu, Oct 7, 2021 at 1:14 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote: > Add SDHI clk mux support to select SDHI clock from different clock > sources. > > As per HW manual, direct clock switching from 533MHz to 400MHz and > vice versa is not recommended. So added support for handling this > in mux. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- > This patch depend upon [1] > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210928130132.15022-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/ > > v1->v2: > * Removed flags and mux flags > * Added readl_poll_timeout to check CPG_CLKSTATUS.SELSDHIx_STS bit > * Added curly braces around val in rzg2l_cpg_sd_clk_mux_get_parent() Thanks for the update! Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> i.e. will queue in renesas-clk-for-v5.16. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
