Add SDHI clock and reset entries in cpg driver. As per the HW manual, we should not directly switch from 533 MHz to 400 MHz and vice versa. To change the setting from 533 MHz to 400 MHz or vice versa, Switch to 266 MHz first,and then switch to the target setting 533 MHz or 400 MHz. So added support in mux to handle this condition. This patch series depend upon [1] [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210928130132.15022-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/ v1->v2: * Removed flags and mux flags from DEF_SD_MUX * Added readl_poll_timeout to check CPG_CLKSTATUS.SELSDHIx_STS bit * Added curly braces around val in rzg2l_cpg_sd_clk_mux_get_parent() * Renamed the clk source names as per latest HW manual * Changed the mult/divider values for 533MHz clock Biju Das (2): drivers: clk: renesas: rzg2l-cpg: Add SDHI clk mux support drivers: clk: renesas: r9a07g044-cpg: Add SDHI clock and reset entries drivers/clk/renesas/r9a07g044-cpg.c | 36 +++++++++ drivers/clk/renesas/rzg2l-cpg.c | 119 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 16 ++++ 3 files changed, 171 insertions(+) -- 2.17.1
