Hi Sergey,
Thanks for the comments
> Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC
>
> Hello!
>
> On 10/1/21 6:06 PM, Biju Das wrote:
>
> > Initialize GbEthernet DMAC found on RZ/G2L SoC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > ---
> > RFC->v1:
> > * Removed RIC3 initialization from DMAC init, as it is
> > same as reset value.
>
> I'm not sure we do a reset everytime...
>
> > * moved stubs function to earlier patches.
> > * renamed "rgeth" with "gbeth"
> > ---
> > drivers/net/ethernet/renesas/ravb.h | 3 ++-
> > drivers/net/ethernet/renesas/ravb_main.c | 30
> > +++++++++++++++++++++++-
> > 2 files changed, 31 insertions(+), 2 deletions(-)
> >
> [...]
> > diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> > b/drivers/net/ethernet/renesas/ravb_main.c
> > index dc817b4d95a1..5790a9332e7b 100644
> > --- a/drivers/net/ethernet/renesas/ravb_main.c
> > +++ b/drivers/net/ethernet/renesas/ravb_main.c
> > @@ -489,7 +489,35 @@ static void ravb_emac_init(struct net_device
> > *ndev)
> >
> > static int ravb_dmac_init_gbeth(struct net_device *ndev) {
> > - /* Place holder */
> > + int error;
> > +
> > + error = ravb_ring_init(ndev, RAVB_BE);
> > + if (error)
> > + return error;
> > +
> > + /* Descriptor format */
> > + ravb_ring_format(ndev, RAVB_BE);
> > +
> > + /* Set AVB RX */
>
> AVB? We don't have it, do we?
Good catch. I Will update the comment in next RFC patch.
>
> > + ravb_write(ndev, 0x60000000, RCR);
>
> Not even RCR.EFFS? And what do bits 29..30 mean?
RZ/G2L Bit 31 is reserved.
Bit 16:30 Reception fifo critical level.
Bit 15:1 reserved
Bit 0 : EFFS
I am not sure, where do you get 29..30? can you please clarify.
>
> [...]
> > + /* Set FIFO size */
> > + ravb_write(ndev, 0x00222200, TGC);
>
> Do TBD<n> (other than TBD0) fields even exist?
Only TBD (Bit 8..9) is available to write, rest all are reserved with remaining values
as in "0x00222200"
Regds,
Biju
>
> [...]
>
> MBR, Sergey
