Hi Biju,
On Thu, Jun 24, 2021 at 3:03 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> RZ/G2L SoC's have different definitions for clock and reset.
> Separate reset from module clocks in order to handle it efficiently.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/clk/renesas/renesas-rzg2l-cpg.h
> +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h
> @@ -99,6 +99,26 @@ struct rzg2l_mod_clk {
> .reset = (_reset) \
> }
>
> +/**
> + * struct rzg2l_reset - Reset definitions
> + *
> + * @id: reset index in array containing all resets
> + * @off: register offset
> + * @reset: reset bits
bit
> + */
> +struct rzg2l_reset {
> + unsigned int id;
Do you need this field? It seems to be set only.
> + u16 off;
> + u8 reset;
> +};
> +
> +#define DEF_RST(_id, _off, _reset) \
> + [_id] = { \
> + .id = _id, \
> + .off = (_off), \
> + .reset = (_reset) \
> + }
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
