RZ/G2L SoC's have different definitions for clock and reset.
Separate reset from module clocks in order to handle it efficiently.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
v2:
* New patch
---
drivers/clk/renesas/renesas-rzg2l-cpg.c | 1 +
drivers/clk/renesas/renesas-rzg2l-cpg.h | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.c b/drivers/clk/renesas/renesas-rzg2l-cpg.c
index 892392b9e0b2..c969c31d4197 100644
--- a/drivers/clk/renesas/renesas-rzg2l-cpg.c
+++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c
@@ -78,6 +78,7 @@ struct rzg2l_cpg_priv {
struct clk **clks;
unsigned int num_core_clks;
unsigned int num_mod_clks;
+ unsigned int num_resets;
unsigned int last_dt_core_clk;
struct raw_notifier_head notifiers;
diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.h b/drivers/clk/renesas/renesas-rzg2l-cpg.h
index a6a3bade1985..10beb1913363 100644
--- a/drivers/clk/renesas/renesas-rzg2l-cpg.h
+++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h
@@ -99,6 +99,26 @@ struct rzg2l_mod_clk {
.reset = (_reset) \
}
+/**
+ * struct rzg2l_reset - Reset definitions
+ *
+ * @id: reset index in array containing all resets
+ * @off: register offset
+ * @reset: reset bits
+ */
+struct rzg2l_reset {
+ unsigned int id;
+ u16 off;
+ u8 reset;
+};
+
+#define DEF_RST(_id, _off, _reset) \
+ [_id] = { \
+ .id = _id, \
+ .off = (_off), \
+ .reset = (_reset) \
+ }
+
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
*
@@ -127,6 +147,10 @@ struct rzg2l_cpg_info {
unsigned int num_mod_clks;
unsigned int num_hw_mod_clks;
+ /* Resets */
+ const struct rzg2l_reset *resets;
+ unsigned int num_resets;
+
/* Critical Module Clocks that should not be disabled */
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
--
2.17.1
