Hi Biju,
On Fri, Jun 11, 2021 at 3:46 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Add clock entries for USB{0,1}.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -88,6 +88,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
> DEF_MOD("dmac", R9A07G044_CLK_DMAC,
> R9A07G044_CLK_P1,
> 0x52c, (BIT(0) | BIT(1)), (BIT(0) | BIT(1))),
> + DEF_MOD("usb0", R9A07G044_CLK_USB0,
> + R9A07G044_CLK_P1,
> + 0x578, (BIT(0) | BIT(2) | BIT(3)), (BIT(0) | BIT(2) | BIT(3))),
> + DEF_MOD("usb1", R9A07G044_CLK_USB1,
> + R9A07G044_CLK_P1,
> + 0x578, (BIT(1) | BIT(3)), (BIT(1) | BIT(3))),
> DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
> R9A07G044_CLK_P0,
> 0x584, BIT(0), BIT(0)),
While the above matches the datasheet, I see a problem with the
implementation. As BIT(3) of the CPG_{CLKON,CLKMON,RST}_USB is shared by
the two USB2.0 channels, disabling USB_PCLK or asserting USB_PRESETN
will affect both channels. So it looks like you need special handling
to make sure that doesn't happen while the other channel is in use.
Or am I missing something?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
