Re: [PATCH v2 4/5] pinctrl: renesas: Initial R8A779A0 (V3U) PFC support

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I got a correct report from a build bot:

> +	{ PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) {
> +		[ 0] = RCAR_GP_PIN(9,  0),	/* AVB5_RX_CTL */
> +		[ 1] = RCAR_GP_PIN(9,  1),	/* AVB5_RXC */
> +		[ 2] = RCAR_GP_PIN(9,  2),	/* AVB5_RD0 */
> +		[ 3] = RCAR_GP_PIN(9,  3),	/* AVB5_RD1 */
> +		[ 4] = RCAR_GP_PIN(9,  4),	/* AVB5_RD2 */
> +		[ 5] = RCAR_GP_PIN(9,  5),	/* AVB5_RD3 */
> +		[ 6] = RCAR_GP_PIN(9,  6),	/* AVB5_TX_CTL */
> +		[ 7] = RCAR_GP_PIN(9,  7),	/* AVB5_TXC */
> +		[ 8] = RCAR_GP_PIN(9,  8),	/* AVB5_TD0 */
> +		[ 9] = RCAR_GP_PIN(9,  9),	/* AVB5_TD1 */
> +		[10] = RCAR_GP_PIN(9, 10),	/* AVB5_TD2 */
> +		[11] = RCAR_GP_PIN(9, 11),	/* AVB5_TD3 */
> +		[12] = RCAR_GP_PIN(9, 12),	/* AVB5_TXCREFCLK */
> +		[13] = RCAR_GP_PIN(9, 13),	/* AVB5_MDIO */
> +		[14] = RCAR_GP_PIN(9, 14),	/* AVB5_MDC */
> +		[15] = RCAR_GP_PIN(9, 15),	/* AVB5_MAGIC */
> +		[16] = RCAR_GP_PIN(9, 16),	/* AVB5_PHY_INT */
> +		[17] = RCAR_GP_PIN(9, 17),	/* AVB5_LINK */
> +		[18] = RCAR_GP_PIN(9, 18),	/* AVB5_AVTP_MATCH */
> +		[19] = RCAR_GP_PIN(9, 19),	/* AVB5_AVTP_CAPTURE */
> +		[20] = RCAR_GP_PIN(9, 20),	/* AVB5_AVTP_PPS */
> +		[21] = SH_PFC_PIN_NONE,
> +		[22] = SH_PFC_PIN_NONE,
> +		[23] = SH_PFC_PIN_NONE,
> +		[24] = SH_PFC_PIN_NONE,
> +		[25] = SH_PFC_PIN_NONE,
> +		[26] = SH_PFC_PIN_NONE,
> +		[27] = SH_PFC_PIN_NONE,
> +		[28] = SH_PFC_PIN_NONE,
> +		[29] = SH_PFC_PIN_NONE,
> +		[30] = SH_PFC_PIN_NONE,
> +		[31] = SH_PFC_PIN_NONE,
> +		[21] = SH_PFC_PIN_NONE,
> +		[22] = SH_PFC_PIN_NONE,
> +		[23] = SH_PFC_PIN_NONE,
> +		[24] = SH_PFC_PIN_NONE,
> +		[25] = SH_PFC_PIN_NONE,
> +		[26] = SH_PFC_PIN_NONE,
> +		[27] = SH_PFC_PIN_NONE,
> +		[28] = SH_PFC_PIN_NONE,
> +		[29] = SH_PFC_PIN_NONE,
> +		[30] = SH_PFC_PIN_NONE,
> +		[31] = SH_PFC_PIN_NONE,
> +	} },

Pins 21-31 are set to none twice.

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