Hi Sergei-san, > From: Sergei Shtylyov, Sent: Wednesday, October 9, 2019 5:58 PM > > On 09.10.2019 11:54, Yoshihiro Shimoda wrote: > > >>> According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register > >>> should be written to 0 because the register is set to 1 on reset. > >> > >> The bit 0 set to 1, not the whole register (it has 1s also in the > >> bits 16-23). > > > > Thank you for the comment. So, I'll fix the commit log as following. > > Is it acceptable? > > > > --- > > According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register > > should be written to 0 because the bit 0 is set to 1 on reset. > > To avoid unexpected behaviors from this incorrect setting, this > > patch fixes it. > > Alright now. Thanks! Best regards, Yoshihiro Shimoda
