On 09.10.2019 7:03, Yoshihiro Shimoda wrote:
According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register
should be written to 0 because the register is set to 1 on reset.
The bit 0 set to 1, not the whole register (it has 1s also in the
bits 16-23).
To avoid unexpected behaviors from this incorrect setting, this
patch fixes it.
Fixes: b3327f7fae66 ("PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot")
Cc: <stable@xxxxxxxxxxxxxxx> # v4.9+
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
[...]
MBR, Sergei
