On Tue, Jun 11, 2019 at 05:02:52PM +0300, Laurent Pinchart wrote:
> Hello,
>
> On Tue, Jun 11, 2019 at 02:30:27PM +0200, Simon Horman wrote:
> > + Laurent
> >
> > On Sun, Jun 09, 2019 at 09:43:18PM +0900, Yoshihiro Kaneko wrote:
> > > From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> > >
> > > Since the R8A77990 SoC uses DU{0,1}, the range from the base address to
> > > the 0x4000 address is used.
> > > This patch fixed it.
> > >
> > > Fixes: 13ee2bfc5444 ("arm64: dts: renesas: r8a77990: Add display output support")
> > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> > > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@xxxxxxxxx>
> >
> > Thanks,
> >
> > This looks fine to me but I will wait to see if there are other reviews
> > before applying.
> >
> > Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
Thanks, I have applied this for inclusion in v5.3.
> > Is a similar fix also appropriate for D3 (r8a77995)
>
> Yes it is.
Nice.
Kaneko-san, could you prepare a patch?
> > And a variant that reduces the register size to 0x5000
> > for M3-W (r8a77965).
>
> M3-W has registers at 0xfeb60000. You could reduce the size from
> 0x80000 to 0x70000 but I don't think it's worth it.
Got it, lets leave M3-W as is.
...
