+ Laurent
On Sun, Jun 09, 2019 at 09:43:18PM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
>
> Since the R8A77990 SoC uses DU{0,1}, the range from the base address to
> the 0x4000 address is used.
> This patch fixed it.
>
> Fixes: 13ee2bfc5444 ("arm64: dts: renesas: r8a77990: Add display output support")
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@xxxxxxxxx>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
Is a similar fix also appropriate for D3 (r8a77995)
And a variant that reduces the register size to 0x5000
for M3-W (r8a77965).
> ---
>
> This patch is based on the devel branch of Simon Horman's renesas tree.
>
> arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> index 547e970..9b15da1 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -1760,7 +1760,7 @@
>
> du: display@feb00000 {
> compatible = "renesas,du-r8a77990";
> - reg = <0 0xfeb00000 0 0x80000>;
> + reg = <0 0xfeb00000 0 0x40000>;
> interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 724>,
> --
> 1.9.1
>
