Hi Geert,
On Mon, Apr 29, 2019, Geert Uytterhoeven wrote:
> On Mon, Apr 29, 2019 at 2:21 PM Chris Brandt <Chris.Brandt@xxxxxxxxxxx>
> wrote:
> > I've been hacking this support into the standard GIC driver in our BSPs
> > for years now. :o
>
> Yeah, and having that patch in your tree breaks all other GICs, as
> I found out the hard way ;-)
I never said it was a good hack :)
> So for RZ/A2, I think it's best to use
>
> compatible = "renesas,r7s9210-irqc", "renesas,rza1-irqc";
> renesas,gic-spi-base = <4>;
That seems to make sense. It's specific to r7s9210 (RZ/A2), but
compatible with the original version which was for rza1. It explains the
history.
> > Side note, I've seen this interrupt pin HW in some older SH4A devices
> > (like SH7724 and SH7757). So it's been around for a while.
>
> Right:
>
> arch/sh/kernel/cpu/sh4a/setup-sh7343.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
> arch/sh/kernel/cpu/sh4a/setup-sh7366.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
> arch/sh/kernel/cpu/sh4a/setup-sh7722.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
> arch/sh/kernel/cpu/sh4a/setup-sh7723.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
> arch/sh/kernel/cpu/sh4a/setup-sh7724.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
>
> However, according to the sh7724 documentation, the register set is
> slightly different, as is its sense configuration (no support for both
> edges, but support for high-level interrupts).
If I remember correctly, I think the design engineers can choose the
sense as they wire it up internally. The ones in the SH7757 were chosen
based on a specific use case. So far, the ones chosen for the RZ/A1 seem to
make everyone happy, so I assume we'll keep them that way.
Chris
