Hi Biju-san, Thank you for the patch! > From: Biju Das, Sent: Monday, April 1, 2019 9:54 PM <snip> > +/******* USB2.0 Host registers (original offset is +0x100) *******/ > +#define USB2_INT_ENABLE 0x100 > +#define USB2_SPD_RSM_TIMSET 0x20c > +#define USB2_OC_TIMSET 0x210 > + > +#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) > +#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) > +#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_USBH_INTB_EN | \ > + USB2_INT_ENABLE_USBH_INTA_EN) > + > +#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b > +#define USB2_OC_TIMSET_INIT 0x000209ab I should have notice this codes at the previous patch though, I'm thinking we can reuse the R-Car Gen3 codes because these values are similar with the phy-rcar-gen3-usb2.c like below: ---------------------------------------------------------------------- /* INT_ENABLE */ #define USB2_INT_ENABLE_UCOM_INTEN BIT(3) #define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) #define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) #define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_UCOM_INTEN | \ USB2_INT_ENABLE_USBH_INTB_EN | \ USB2_INT_ENABLE_USBH_INTA_EN) <snip> /* SPD_RSM_TIMSET */ #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b /* OC_TIMSET */ #define USB2_OC_TIMSET_INIT 0x000209ab ---------------------------------------------------------------------- If so, we can use ehci-platform.c and ohci-platform.c as-is. In this case, the "phy: renesas: phy-rcar-gen2: Add support for r8a77470" driver should be initialized at first to release PLLRESET. And then, the phy-rcar-gen3-usb2 driver would be initialized as second step. I think we can set these resisters at phy_init timing because the following patch did so: https://patchwork.kernel.org/patch/10655855/ What do you think? Best regards, Yoshihiro Shimoda
