Hello!
On 03/27/2019 04:32 AM, masonccyang@xxxxxxxxxxx wrote:
>> >>>> +static void rpc_spi_mem_set_prep_op_cfg(struct spi_device *spi,
>> >>>> + const struct spi_mem_op *op,
>> >>>> + u64 *offs, size_t *len)
>> >>>> +{
>> >>>> + struct rpc_spi *rpc = spi_controller_get_devdata(spi->controller);
>> >>>
>> >>>> + if (op->dummy.nbytes) {
>> >>>> + rpc->smenr |= RPC_SMENR_DME;
>> >>>> + rpc->dummy = RPC_SMDMCR_DMCYC(op->dummy.nbytes);
>> >>>
>> >>> SMDMCR.DMCYC is in bits -- you forgot to multiply by 8.
>> >>
>> >> ?
>> >>
>> >> It's dummy cycles setting, i.e,. 0 is 1 cycle dummy and
>> >
>> > Yeah, I should've written "cycles", sorry about that.
>>
>> I also should've mentioned that w/o this change the "read SFDP" command
>> returns garbage and the flash doesn't work.
>>
>
> Have you checked the dummy cycles setting with logical analysis ?
I don't have a logic analyzer (if you meant it). However, I dumped all the registers
in your driver and Cogent's own driver, and SMDMCR was set to 0 in your driver and to
7 in our driver -- and only our driver then worked correctly.
> As datasheet mentioned it's dummy cycles depends on the transfer bit size setting = 1, 4 or 8.
> Setting RPC_SMDMCR_DMCYC(0x13) in 8 bits data width I got a 20 dummy cycles.
> Also confirmed these 20 dummy cycles by logical analysis equipment.
[...]
> best regards,
> Mason
MBR, Sergei
