Hi Simon,
On Thu, Feb 28, 2019 at 2:52 PM Simon Horman <horms+renesas@xxxxxxxxxxxx> wrote:
> Adds support for R-Car E3 (r8a77990) ZG clock.
>
> Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
> ---
> Tested on Ebisu to the extent that the clock rate is 600MHz on boot
> ---
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 ++
> drivers/clk/renesas/rcar-gen3-cpg.c | 1 -
> drivers/clk/renesas/rcar-gen3-cpg.h | 1 +
> 3 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> index 0e475dcb68b9..d0d29fc942ff 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -83,6 +83,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
> DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
> DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0,
> 4, CPG_FRQCRC, 8),
> + DEF_GEN3_Z("zg", R8A77990_CLK_ZG, CLK_TYPE_GEN3_Z, CLK_PLL0,
> + 8, CPG_FRQCRB, 24),
While this approach may be correct for R-Car H3, M3-W, and M3-N, this is
not correct for R-Car E3, due to the presence of Spread Spectrum Clock
Generator support:
- When SCCG is enabled (MD12=1), the parent clock is either S0 or S1,
with only 2 or 3 (out of 32) supported dividers,
- When SCCG is disabled (MD12=0), the parent clock is PLL0, with only
2 (out of 32) supported dividers.
So I'm afraid the ZG clock on SCCG-capable SoCs needs its own very special
clock type.
This applies also to R-Car D3 and RZ/G2E.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
