Adds support for R-Car E3 (r8a77990) ZG clock.
Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
---
Tested on Ebisu to the extent that the clock rate is 600MHz on boot
---
drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 ++
drivers/clk/renesas/rcar-gen3-cpg.c | 1 -
drivers/clk/renesas/rcar-gen3-cpg.h | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 0e475dcb68b9..d0d29fc942ff 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -83,6 +83,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0,
4, CPG_FRQCRC, 8),
+ DEF_GEN3_Z("zg", R8A77990_CLK_ZG, CLK_TYPE_GEN3_Z, CLK_PLL0,
+ 8, CPG_FRQCRB, 24),
DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 14a82c51682e..0d0e698442e2 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -70,7 +70,6 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
* rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
* parent - fixed parent. No clk_set_parent support
*/
-#define CPG_FRQCRB 0x00000004
#define CPG_FRQCRB_KICK BIT(31)
struct cpg_z_clk {
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 02bf3785263c..9525df8a835c 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -68,6 +68,7 @@ struct rcar_gen3_cpg_pll_config {
u8 osc_prediv;
};
+#define CPG_FRQCRB 0x004
#define CPG_FRQCRC 0x0e0
#define CPG_RCKCR 0x240
--
2.11.0
