Hi Simon,
On Thu, Jan 31, 2019 at 10:40 AM Simon Horman
<horms+renesas@xxxxxxxxxxxx> wrote:
> Parameterise the offset of control bits within the FRQCRC register
> for Z and Z2 clocks.
>
> This is in preparation for supporting the Z2 clock on the R-Car E3
> (r8a77990) SoC which uses a different offset for control bits to
> other, already, supported SoCs.
>
> This mechanism should be extendable to other clocks, such as ZG,
> f.e. by adding the number of control bits as a parameter to
> cpg_z_clk_register().
>
> As suggested by Geert Uytterhoeven.
>
> Signed-off-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -568,14 +566,9 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
> break;
>
> case CLK_TYPE_GEN3_Z:
> - return cpg_z_clk_register(core->name, __clk_get_name(parent),
> - base, CPG_FRQCRC_ZFC_MASK,
> - core->div);
> -
> case CLK_TYPE_GEN3_Z2:
> return cpg_z_clk_register(core->name, __clk_get_name(parent),
> - base, CPG_FRQCRC_Z2FC_MASK,
> - core->div);
> + base, core->div, core->offset);
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 are now the same type.
Perhaps they can be merged completely, and be absorbed into the
DEF_GEN3_Z() macro?
Or not, depending on how ZG support will be added...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
