Hi Simon,
On Thu, Jan 31, 2019 at 10:40 AM Simon Horman
<horms+renesas@xxxxxxxxxxxx> wrote:
> this series adds the R-Car E3 (r8a77990) Z2 clock as a clock
> with both a fixed and variable divisor with a parent of PLL0.
>
> In order to do so this series:
>
> 1. Parameterise Z and Z2 clock fixed divisor in shared Gen-3 CPG
> driver code to allow fixed divisors other than 2 - the E3 Z2
> clock has a fixed divisor of 4
>
> 2. Parameterise offset of Z and Z2 clock controll bits -
> the offsets on E3 differ to other R-Car Gen 3 SoCs
>
> 3. Support Z and Z2 clocks with high frequency parents.
> The parent of the E3 Z2 clock, PLL0, is 4.8GHz and thus
> when expressed in HZ must be treated as a 64bit value.
>
> 4. Actually add the E3 Z2 clock
>
> As a follow-up, as per reading the documentation, the RZ/G2E (r8a774c0)
> Z2 clock is added.
Thanks, this looks good to me.
Before queuing in clk-renesas-v5.1, to allow more testing, I'm importing
this into a topic branch, to be included in today's renesas-drivers release.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
