On Fri, Jan 11, 2019 at 12:50:20PM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
>
> MOD_SEL register bit numbering was different from R-Car D3 SoC and
> R-Car H3/M3-[WN] SoCs.
>
> MOD_SEL 1-bit H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'0 b'0
> Set Value = H'1 b'1 b'1
>
> MOD_SEL 2-bits H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'00 b'00
> Set Value = H'1 b'01 b'10
> Set Value = H'2 b'10 b'01
> Set Value = H'3 b'11 b'11
>
> MOD_SEL 3-bits H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'000 b'000
> Set Value = H'1 b'001 b'100
> Set Value = H'2 b'010 b'010
> Set Value = H'3 b'011 b'110
> Set Value = H'4 b'100 b'001
> Set Value = H'5 b'101 b'101
> Set Value = H'6 b'110 b'011
> Set Value = H'7 b'111 b'111
>
> This patch replaces the #define name and value of MOD_SEL.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support")
> [shimoda: split a patch per SoC and revise the commit log]
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> [geert: Use a macro to do the actual reordering]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> Untested as we don't know how to test the impact of MOD_SEL bits on
> output pins.
>
> Using a macro makes the code easier to write, read, and maintain.
> Use "git show --color-words" to see the difference.
>
> I'd love to handle the reversal in the PINMUX_CFG_REG_VAR()
> descriptions, but I can't use e.g. REV4(MOD_SEL0_24_23) there, as
> MOD_SEL0_24_23 is a single parameter, not 4 parameters.
>
> Can this be improved?
Likely but nothing springs to mind.
Reviewed-by: Simon Horman <horms+renesas@xxxxxxxxxxxx>
