Re: [PATCH v2 2/2] clk: renesas: rcar-gen3: add HS400 quirk for SD clock

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Hi Wolfram,

On Fri, Nov 30, 2018 at 12:47 PM Wolfram Sang <wsa@xxxxxxxxxxxxx> wrote:
> > That should have been rate :-) To elaborate a bit more:
> >
> > The patch is different from v1 as a different approach to solve the
> > issue have been found. Instead of only ignoring the first row of the
> > list of possible settings when selecting which divider to use also
> > ignore it when examining which state the hardware is in. That is the
> > driver is no longer aware the first row exists with this patch.
> >
> > This was in v1 not possible as the first row might be a state the
> > bootloader left the hardware in and then the clock failed to register as
> > it would need to update its own state to match the hardware.
> >
> > As the driver needed to know about the state the hardware was in when
> > probing but not use it when selecting a divider the more complex v1 was
> > needed. When selecting a divider we wish for it to select the second
> > option for the divider value '4' when running on a SoC which needs the
> > quirk.
> >
> > With v2 which depends on [1] this is not needed as the clock driver now
> > sets a know state when registering the clock so this patch can be made
> > much simpler by simply 'removing' the first row from all operations.
>
> Thanks for the elaboration. I still think the above is the way to go and
> I still wonder a little why it was implemented differently beforehand.

Probably the initial implementation didn't care at all about selecting clock
speeds (no fancy SDR/HS modes supported), so just used whatever U-Boot
had set up.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds



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