RE: [PATCH 1/2] ARM: dts: r7s9210: Initial SoC device tree

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Hi Simon,


On Friday, November 30, 2018, Simon Horman wrote:
> > +	cpg: clock-controller@fcfe0020 {
> > +		compatible = "renesas,r7s9210-cpg-mssr";
> > +		reg = <0xfcfe0010 0x455>;
> 
> There is a discrepancy here between the base address, fcfe0020
> and the start address of the register range, 0xfcfe0010.

Good catch! Thank you.


> > +	ostm0: timer@e803b000 {
> > +		compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> > +		reg = <0xe803b000 0x30>;
> 
> 
> Its not clear to me why the size of the register range is 0x30.

Because when reviewing the bindings docs, I was putting in 'exact' 
values, but Geert said "those are ugly, just round up to make it look
nicer".
So instead of 0x21, I put 0x30.

You know...the standard answer: Throw Geert under the bus ;)


Chris





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