Hi Marek,
On Wed, Nov 21, 2018 at 12:33 AM Marek Vasut <marek.vasut@xxxxxxxxx> wrote:
> On 11/19/2018 10:47 AM, Geert Uytterhoeven wrote:
> > On Mon, Nov 19, 2018 at 10:06 AM Geert Uytterhoeven
> > <geert@xxxxxxxxxxxxxx> wrote:
> >> On Sun, Nov 18, 2018 at 6:29 PM Marek Vasut <marek.vasut@xxxxxxxxx> wrote:
> >>> From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> >>>
> >>> This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990
> >>> SoC.
> >>>
> >>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
> >>> Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxx>
> >>
> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> >> i.e. will queue in sh-pfc-for-v4.21.
> >
> > Upon second look, the canfd groups and functions should be moved from
> > the common to the automotive section, as RZ/G2E does not have them.
> > As I have to update the array sizes anyway (my branch already has more
> > patches applied), I moved them while applying.
> >
> > Please check the result later today, after I have pushed.
>
> Looks OK to me. Incrementing the array sizes in the driver is kinda icky
Thanks!
> though.
Unfortunately I see no way to avoid that, as both arrays need to be consecutive
in memory. Do you see a better solution?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
