RE: [PATCH] arm64: dts: renesas: revise properties for usb 2.0

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Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Thursday, September 6, 2018 7:19 PM
> 
> Hi Shimoda-san,
> 
> On Thu, Sep 6, 2018 at 12:09 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > > From: Geert Uytterhoeven, Sent: Wednesday, September 5, 2018 9:59 PM
> > > On Fri, Aug 31, 2018 at 10:22 AM Yoshihiro Shimoda
> > > <yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > > > R-Car Gen3 needs to enable/deassert clocks/resets of both usb 2.0
> > > > host (included phy) and peripheral. Otherwise, other side device
> > > > cannot work correctly. So, this patch revises properties of clocks
> > > > and resets. After that, each device driver can enable/deassert
> > > > clocks/resets by its self.
> > > >
> > > > Notes:
> > > >  - To work the renesas_usbhs driver correctly when host side drivers
> > > >    are disabled and the renesas_usbhs driver doesn't have multiple
> > > >    clock management, this patch doesn't change the order of the clocks
> > > >    property in each hsusb node.
> > > >  - This patch doesn't have any side-effects even if the renesas_usbhs
> > > >    driver doesn't have reset_control and multiple clock management.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > >
> > > Thanks for your patch!
> > >
> > > I'm a bit confused about the HS-USB <-> EHCI/OHCI topology.
> > > Can you please explain?
> > >
> > > Thanks!
> >
> > HS-USB <-> EHCI/OHCI topology on R-Car H3 is:
> >
> >  EHCI/OHCI ch0/3 ---+--- PHY (is included on the EHCI/OHCI) --- External pins
> >  HS-USB ch0/3    ---+
> >
> >  EHCI ch1/2      ------- PHY (is included on the EHCI/OHCI) --- External pins
> >  # These channels don't have HS-USB.
> 
> Thanks, that's the part is missed, and couldn't find immediately in the
> HW manual.

That's true...

> So HS-USB is the usb device ("gadget") part, and EHCI/OHCI is the
> usb host part?

That's right.

> >
> > And module stops and resets of HS-USB and EHCI/OHCI topology on R-Car H3 is:
> >
> >  MSTP/RST703 ---+(OR)---+--- EHCI/OHCI ch0
> >  MSTP/RST704 ---+       +--- HS-USB ch0
> >
> >  MSTP/RST702 --------------- EHCI/OHCI ch1
> >  MSTP/RST701 --------------- EHCI/OHCI ch2
> >
> >  MSTP/RST700 ---+(OR)---+--- EHCI/OHCI ch3
> >  MSTP/RST705 ---+       +--- HS-USB ch3
> >
> > Should I describe these topology on the commit log or somewhere?
> 
> Yes, I think that would be helpful.

I got it. I'll submit v2 patch tomorrow or later.

Best regards,
Yoshihiro Shimoda

> Thanks!
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds




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