According to revision 1.00 of R-Car Gen3 Soc manual, setting bits
PnMR[13:12] is only valid if the DU group has two channels.
It is then valid writing to PnMR[13:12] for:
R-Car H3 = DU group 0 and DU group 1
R-Car M3-W, M3-N: DU group 0 only
R-Car D3/E3: DU group 0 (no group 1)
It is always invalid writing PnMR[13:12] on:
R-Car V3M/V3H: only group 0 is present, but with a single channel
Signed-off-by: Jacopo Mondi <jacopo+renesas@xxxxxxxxxx>
---
drivers/gpu/drm/rcar-du/rcar_du_plane.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
index 5c2462a..647d2fc 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
@@ -505,8 +505,17 @@ static void rcar_du_plane_setup_format_gen3(struct rcar_du_group *rgrp,
unsigned int index,
const struct rcar_du_plane_state *state)
{
- rcar_du_plane_write(rgrp, index, PnMR,
- PnMR_SPIM_TP_OFF | state->format->pnmr);
+ u32 mask = BIT(rgrp->index * 2) | BIT(rgrp->index * 2 + 1);
+ u32 pnmr = PnMR_SPIM_TP_OFF;
+
+ /*
+ * Setting PnMR[13:12] is only allowed when more than 1 channel is
+ * availble in the group.
+ */
+ if ((rgrp->channels_mask & mask) == mask)
+ pnmr |= state->format->pnmr;
+
+ rcar_du_plane_write(rgrp, index, PnMR, pnmr);
rcar_du_plane_write(rgrp, index, PnDDCR4,
state->format->edf | PnDDCR4_CODE);
--
2.7.4
