Hi! This series adds CPU idle support for H3 and M3-W. It's a straight up-port from the BSP. The part that disables cpuidle for the CA53 cores on M3ULCB is a bit dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0 SoC? CU Uli Dien Pham (2): arm64: dts: r8a7795: Add cpuidle support for CA53 cores arm64: dts: r8a7796: Add cpuidle support for CA53 cores Khiem Nguyen (2): arm64: dts: r8a7795: Add cpuidle support for CA57 cores arm64: dts: r8a7796: Add cpuidle support for CA57 cores Takeshi Kihara (1): arm64: dts: r8a7796-m3ulcb: Disable cpuidle support for CA53 cores arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 ++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 22 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++++ 3 files changed, 84 insertions(+) -- 2.7.4
