Hi Uli,
On Fri, Dec 15, 2017 at 4:14 PM, Ulrich Hecht
<ulrich.hecht+renesas@xxxxxxxxx> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
>
> This patch adds ZG clock for R8A7796 SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@xxxxxxxxxxx>
Forgot to add you're own SoB?
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
> /* Core Clock Outputs */
> DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
> DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
> + DEF_FIXED("zg", R8A7796_CLK_ZG, CLK_PLL4, 4, 1),
Shouldn't this be a variable clock of type CLK_TYPE_GEN3_ZG?
What else is the purpose of "[PATCH 2/4] clk: renesas: rcar-gen3: Add ZG
clock divider support"?
> @@ -117,6 +118,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
> };
>
> static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
> + DEF_MOD("3dge", 112, R8A7796_CLK_ZG),
> DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
> DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
> DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
> --
This part is fine.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
