Hi,
as mentioned previously since ages I'm back looking at the RCar3 status
in recent mainline (4.13-rc7). While doing so, it looks to me that some
msiof fixes from recent BSP
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.9/rcar-3.5.8
are not in mainline, yet. E.g.:
Hiromitsu Yamasaki | spi: sh-msiof: Add registers reset
Hiromitsu Yamasaki | spi: sh-msiof: Fix gpio function
Hiromitsu Yamasaki | spi: sh-msiof: Add MSIOF parent clock changing
function for R-Car Gen3
Hiromitsu Yamasaki | spi: sh-msiof: Wait for Tx FIFO empty after DMA
Ryo Kataoka | spi: sh-msiof: Fix DMA completion
Ryo Kataoka | spi: sh-msiof: Fix MSIOF address for DMAC
Hiromitsu Yamasaki | spi: sh-msiof: Fix DMA transfer size check
Hiromitsu Yamasaki | spi: sh-msiof: Add sleep before master transfer for
test
seem to be needed to make msiof in mainline work reliably on larger files.
Are there any plans to pick these, already? Or, if not, would it be fine
to pick them from the BSP and just submit them here? Or is some major
rework needed?
Best regards
Dirk
