Hi,
as mentioned previously since ages I'm back looking at the RCar3 status
in recent mainline (4.13-rc7). While doing so, it looks to me that some
Z* clock patches from recent BSP
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.9/rcar-3.5.8
are not in mainline clock configuration, yet. E.g.:
Takeshi Kihara | clk: renesas: r8a7795: Add ZG clock
Takeshi Kihara | clk: renesas: r8a7795: Add ZG clock
Takeshi Kihara | clk: renesas: r8a7795: Add Z2 clock
Takeshi Kihara | clk: renesas: r8a7795: Add Z clock
Takeshi Kihara | clk: renesas: rcar-gen3: Adjust output of PLL4 as 3DGE
clock divider input
Takeshi Kihara | clk: renesas: rcar-gen3: Add ZG clock divider support
Dien Pham | clk: renesas: rcar-gen3: Add PLL0 clock errata workaround in
PLL0 clk driver
Dien Pham | clk: renesas: rcar-gen3: Add PLL0 clk driver support
Dien Pham | clk: renesas: rcar-gen3: Adjust output of PLL0, PLL2 as
SYSC-CPUs input
Takeshi Kihara | clk: renesas: rcar-gen3: Add Z2 clock divider support
Takeshi Kihara | clk: renesas: rcar-gen3: Add Z clock divider support
Are there any plans to pick these, already? Or, if not, would it be fine
to pick them from the BSP and just submit them here? Or is some major
rework needed?
Best regards
Dirk
