Hi Marek, Thank you for the patch. On Thursday 12 Jan 2017 02:03:24 Marek Vasut wrote: > Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These > chips have two clock inputs, XTAL or CLK, which are muxed into single > PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip > while the 5P49V5923 requires external XTAL. > > The PLL feeds two fractional dividers. Each fractional divider feeds > output mux, which allows selecting between clock from the fractional > divider itself or from output mux on output N-1. In case of output > mux 0, the output N-1 is instead connected to the output from the mux > feeding the PLL. > > The driver thus far supports only the 5P49V5923 and 5P49V5933, while > it should be easily extensible to the whole 5P49V59xx family of chips > as they are all pretty similar. > > Signed-off-by: Marek Vasut <marek.vasut@xxxxxxxxx> > Cc: Michael Turquette <mturquette@xxxxxxxxxxxx> > Cc: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> > Cc: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx> > Tested-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > Cc: linux-renesas-soc@xxxxxxxxxxxxxxx Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > --- > V2: - Drop address-cells and size-cells from the binding > - Add clock-names to the binding > - Drop vc5_input_names > - Fix assortment of spelling mistakes > - Switch div_frc and div_int datatype to uXX > - Switch f_in to u32 > - Add missing remove > - Define macros for handling XIN and CLKIN > - Rework the FOD fractional divider calculation, this was wrong > and made the output clock be off considerably under certain > circumstances (when the fractional part was large). > V3: - Rework the MUX frequency recalculation and divider configration > so that it fits into the clock framework > - Add support for 5P49V5933 chip to lay groundwork for adding more > chips easily. > - Export the OUT0_SEL_I2CB output into the clock framework, so it > can be accessed from DT as well. WARNING: This does change the > bindings, clock0 is now the OUT0_SEL_I2CB, clock1 is OUT1 and > clock2 is OUT2 (or OUT4 on the 5P49V5933). > - Drop unnecessary caching of pin_*_name clock name and clk_hw > structures in driver data. > - Add missing MAINTAINERS entry > V4: - Support also 5P49V5923A by dropping the B from the bindings and > code. According to the update notice, the chips are identical > except for disabling the VCO monitoring, which is internal > factory-defined bit and has no impact on silicon performance. > V5: - Make the CCF handle upstream clock enabling and disabling > - Drop test for unsigned value reg being less than zero > - Streamline vc5_map_index_to_output > V6: - Drop the error message from vc5_of_clk_get(), this will be > reported by the core > --- > MAINTAINERS | 5 + > drivers/clk/Kconfig | 10 + > drivers/clk/Makefile | 1 + > drivers/clk/clk-versaclock5.c | 793 +++++++++++++++++++++++++++++++++++++++ > 4 files changed, 809 insertions(+) > create mode 100644 drivers/clk/clk-versaclock5.c -- Regards, Laurent Pinchart
