On 25/05/16 09:49, Kuninori Morimoto wrote: > > Hi Kieran > >> I have added an initial patch to support the FDP1 in the clock >> framework, but I have not been able to correctly identify the actual >> clock parent. >> >> For now I have assumed that it is R8A7795_CLK_S2D1. >> >> Could you please confirm this selection, or help identify the true >> parent please? > > OK, please wait Thanks, Just to add to this request, could you ask the HW engineers to confirm the clock parents for the FCPF (0,1,2) as well please? They too are currently listed as R8A7795_CLK_S2D1, however now that I am trying to enable the FCPF and read registers from it - the VCR is returning as 0x00 (I expect 0x0101) and then I'm getting "Bad mode in Error handler detected, code 0xbf000002 -- SError" My suspicion is that my clock has not been enabled correctly :) Thanks again for your help -- Regards Kieran Bingham
