> > @@ -114,8 +117,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
> > DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
> > DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
> >
> > - DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, 0x0240, 8),
> > - DEF_DIV6_RO("r_int", R8A7795_CLK_RINT, CLK_EXTAL, 0x0240, 32),
> > + DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
> > + DEF_DIV6_RO("r_int", R8A7795_CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
> > +
> > + /* must come after EXTALR because we need its rate */
>
> must come after r_int because we need that clock as a possible parent?
Well, I added the comment because the dependency to EXTALR is not
obvious. Unlike the dependency to RINT which is described in the same
manner as the rest of the clocks.
Maybe I should simply remove the comment if it creates only confusion?
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