Hi Wolfram,
On Thu, Mar 24, 2016 at 2:00 PM, Wolfram Sang <wsa@xxxxxxxxxxxxx> wrote:
> From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
>
> R can select between two parents. We deal with it like this: During
> initialization, check if EXTALR is populated. If so, use it for R. If
> not, use R_Internal. clk_mux doesn't help here because we don't want to
> switch parents depending on the clock rate. The clock rate (and source)
> should stay constant for the watchdog, so I think a setup like this
> during initialization makes sense.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> ---
>
> Since RFC, remove FIXME by using clk_get_rate() via clk.h
>
> drivers/clk/renesas/r8a7795-cpg-mssr.c | 22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index d305bcd3ef6619..c260da5e70e116 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -114,8 +117,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
> DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
> DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
>
> - DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, 0x0240, 8),
> - DEF_DIV6_RO("r_int", R8A7795_CLK_RINT, CLK_EXTAL, 0x0240, 32),
> + DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
> + DEF_DIV6_RO("r_int", R8A7795_CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
> +
> + /* must come after EXTALR because we need its rate */
must come after r_int because we need that clock as a possible parent?
> + DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, R8A7795_CLK_RINT),
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
