Hi Wolfram,
On Thu, Mar 17, 2016 at 10:54 PM, Wolfram Sang <wsa@xxxxxxxxxxxxx> wrote:
> From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
>
> Hard code the RCLK to make the watchdog usable for testing.
>
> I am not sure where to put the selectable parent clock in DT. It can be
> the internal RCLK or EXTALR. Also, the fixed divider value depends on
> mode pins and should be read from the register, too.
EXTALR is already in DT.
I don't think we need the internal RCLK in DT.
It should be handled internally in the r8a7795-cpg-mssr drivers.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
