From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
Hard code the RCLK to make the watchdog usable for testing.
I am not sure where to put the selectable parent clock in DT. It can be
the internal RCLK or EXTALR. Also, the fixed divider value depends on
mode pins and should be read from the register, too.
Not-really-Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
---
drivers/clk/shmobile/r8a7795-cpg-mssr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c
index b2198aef5ed429..3c10d9d11314ed 100644
--- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c
+++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c
@@ -109,6 +109,8 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
+ //FIXME: divisor depends on MD13+14. Input can be CLK_EXTALR, too.
+ DEF_FIXED("rclk", R8A7795_CLK_R, CLK_EXTAL, 1024, 1),
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
@@ -139,6 +141,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
+ DEF_MOD("rwdt0", 402, R8A7795_CLK_R),
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
--
2.7.0
