On Thu, Jan 07, 2021 at 10:30:20AM +0800, Tzung-Bi Shih wrote: > The register MT8192_CORE0_MEM_ATT_PREDEF contains attributes for each > memory region. It defines whether a memory region can be managed by MPU > or not. > > In the past, due to the default settings in the register, MT8192 SCP > works luckily. After enabling L1TCM, SCP starts to access memory region > that is not included in the default settings. As a result, SCP hangs. > > Enables MPU for all memory regions in MT8192 SCP. > > Note that the register is read only once when SCP resets. Thus, it must > be set from kernel side. Much better - now I understand what is going on. Based on the description of the problem please add a "Fixes" tag and CC stable. I also suggest you bundle this patch with your other patchset [1] once you have make the modifications for devm_platform_ioremap_resource_byname(). Thanks, Mathieu [1]. https://patchwork.kernel.org/project/linux-remoteproc/list/?series=401287 > > Signed-off-by: Tzung-Bi Shih <tzungbi@xxxxxxxxxx> > --- > Changes from v1[1]: > - Adds more details in commit message. > > [1]: https://patchwork.kernel.org/project/linux-remoteproc/patch/20201214051047.859110-1-tzungbi@xxxxxxxxxx/ > > drivers/remoteproc/mtk_common.h | 1 + > drivers/remoteproc/mtk_scp.c | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h > index 94bc54b224ee..5f7cd2336cef 100644 > --- a/drivers/remoteproc/mtk_common.h > +++ b/drivers/remoteproc/mtk_common.h > @@ -47,6 +47,7 @@ > > #define MT8192_CORE0_SW_RSTN_CLR 0x10000 > #define MT8192_CORE0_SW_RSTN_SET 0x10004 > +#define MT8192_CORE0_MEM_ATT_PREDEF 0x10008 > #define MT8192_CORE0_WDT_CFG 0x10034 > > #define SCP_FW_VER_LEN 32 > diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c > index f025aba67abc..130c0b9511df 100644 > --- a/drivers/remoteproc/mtk_scp.c > +++ b/drivers/remoteproc/mtk_scp.c > @@ -369,6 +369,9 @@ static int mt8192_scp_before_load(struct mtk_scp *scp) > mt8192_power_on_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN); > mt8192_power_on_sram(scp->reg_base + MT8192_CPU0_SRAM_PD); > > + /* enable MPU for all memory regions */ > + writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); > + > return 0; > } > > -- > 2.29.2.729.g45daf8777d-goog >
