On 2020/11/16 21:47, Leon Romanovsky wrote:
> On Mon, Nov 16, 2020 at 07:58:38PM +0800, Weihang Li wrote:
>> From: Lang Cheng <chenglang@xxxxxxxxxx>
>>
>> Stash is a mechanism that uses the core information carried by the ARM AXI
>> bus to access the L3 cache. It can be used to improve the performance by
>> increasing the hit ratio of L3 cache. CQs need to enable stash by default.
>>
>> Signed-off-by: Lang Cheng <chenglang@xxxxxxxxxx>
>> Signed-off-by: Weihang Li <liweihang@xxxxxxxxxx>
>> ---
>> drivers/infiniband/hw/hns/hns_roce_common.h | 12 +++++++++
>> drivers/infiniband/hw/hns/hns_roce_device.h | 1 +
>> drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 3 +++
>> drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 39 +++++++++++++++++------------
>> 4 files changed, 39 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h
>> index f5669ff..8d96c4e 100644
>> --- a/drivers/infiniband/hw/hns/hns_roce_common.h
>> +++ b/drivers/infiniband/hw/hns/hns_roce_common.h
>> @@ -53,6 +53,18 @@
>> #define roce_set_bit(origin, shift, val) \
>> roce_set_field((origin), (1ul << (shift)), (shift), (val))
>>
>> +#define FIELD_LOC(field_h, field_l) field_h, field_l
>> +
>> +#define _hr_reg_set(arr, field_h, field_l) \
>> + do { \
>> + BUILD_BUG_ON(((field_h) / 32) != ((field_l) / 32)); \
>> + BUILD_BUG_ON((field_h) / 32 >= ARRAY_SIZE(arr)); \
>> + (arr)[(field_h) / 32] |= \
>> + cpu_to_le32(GENMASK((field_h) % 32, (field_l) % 32)); \
>> + } while (0)
>> +
>> +#define hr_reg_set(arr, field) _hr_reg_set(arr, field)
>
> I afraid that it is too much.
Hi Leon,
Thanks for the comments.
> 1. FIELD_LOC() macro to hide two fields.
Jason has suggested us to simplify the function of setting/getting bit/field in
hns driver like IBA_SET and IBA_GET.
https://patchwork.kernel.org/project/linux-rdma/patch/1589982799-28728-3-git-send-email-liweihang@xxxxxxxxxx/
So we try to make it easier and clearer to define a bitfield for developers.
For example:
#define QPCEX_SRC_ID FIELD_LOC(94, 84)
hr_reg_set(context->ext, QPCEX_SRC_ID);
This will set 84 ~ 91 bit of QPC to 1. Without FIELD_LOC(), it may look
like:
#define QPCEX_SRC_ID_START 84
#define QPCEX_SRC_ID_END 94
hr_reg_set(context->ext, QPCEX_SRC_ID_END, QPCEX_SRC_ID_START);
> 2. hr_reg_set and _hr_reg_set are the same.
'field' will be spilted into two parts: 'field_h' and 'field_l':
#define _hr_reg_set(arr, field_h, field_l)
...
#define hr_reg_set(arr, field) _hr_reg_set(arr, field)
> 3. In both patches field_h and field_l are the same.
This is because we want hr_reg_set() to be used both for setting bits and for
setting fields. In this series, we just use it to set bit.
> 4. "do {} while (0)" without need.
OK, I will remove the do-while and replace BUILD_BUG_ON with BUILD_BUG_ON_ZERO:
#define _hr_reg_set(arr, field_h, field_l) \
(arr)[(field_h) / 32] |= \
cpu_to_le32(GENMASK((field_h) % 32, (field_l) % 32)) + \
BUILD_BUG_ON_ZERO(((field_h) / 32) != ((field_l) / 32)) + \
BUILD_BUG_ON_ZERO((field_h) / 32 >= ARRAY_SIZE(arr));
Weihang
>
> Thanks
>
