On Mon, Nov 16, 2020 at 07:58:38PM +0800, Weihang Li wrote:
> From: Lang Cheng <chenglang@xxxxxxxxxx>
>
> Stash is a mechanism that uses the core information carried by the ARM AXI
> bus to access the L3 cache. It can be used to improve the performance by
> increasing the hit ratio of L3 cache. CQs need to enable stash by default.
>
> Signed-off-by: Lang Cheng <chenglang@xxxxxxxxxx>
> Signed-off-by: Weihang Li <liweihang@xxxxxxxxxx>
> ---
> drivers/infiniband/hw/hns/hns_roce_common.h | 12 +++++++++
> drivers/infiniband/hw/hns/hns_roce_device.h | 1 +
> drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 3 +++
> drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 39 +++++++++++++++++------------
> 4 files changed, 39 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h
> index f5669ff..8d96c4e 100644
> --- a/drivers/infiniband/hw/hns/hns_roce_common.h
> +++ b/drivers/infiniband/hw/hns/hns_roce_common.h
> @@ -53,6 +53,18 @@
> #define roce_set_bit(origin, shift, val) \
> roce_set_field((origin), (1ul << (shift)), (shift), (val))
>
> +#define FIELD_LOC(field_h, field_l) field_h, field_l
> +
> +#define _hr_reg_set(arr, field_h, field_l) \
> + do { \
> + BUILD_BUG_ON(((field_h) / 32) != ((field_l) / 32)); \
> + BUILD_BUG_ON((field_h) / 32 >= ARRAY_SIZE(arr)); \
> + (arr)[(field_h) / 32] |= \
> + cpu_to_le32(GENMASK((field_h) % 32, (field_l) % 32)); \
> + } while (0)
> +
> +#define hr_reg_set(arr, field) _hr_reg_set(arr, field)
I afraid that it is too much.
1. FIELD_LOC() macro to hide two fields.
2. hr_reg_set and _hr_reg_set are the same.
3. In both patches field_h and field_l are the same.
4. "do {} while (0)" without need.
Thanks
