[bug report] RDMA/cxgb3: Support the new memory registration API

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[ Old patch is old.  It implies this code is harmless.  Anyway, I'm
  testing some new stuff and trying to get feedback to see if it's
  useful.  - dan ]


Hello Sagi Grimberg,

The patch 14fb4171ab1c: "RDMA/cxgb3: Support the new memory
registration API" from Oct 13, 2015, leads to the following static
checker warning:

	drivers/infiniband/hw/cxgb3/iwch_qp.c:173 build_memreg()
	warn: dead code because of 'i == 10' and 'i < mhp->npages'

drivers/infiniband/hw/cxgb3/iwch_qp.c
   149  static int build_memreg(union t3_wr *wqe, struct ib_reg_wr *wr,
   150                            u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
   151  {
   152          struct iwch_mr *mhp = to_iwch_mr(wr->mr);
   153          int i;
   154          __be64 *p;
   155  
   156          if (mhp->npages > T3_MAX_FASTREG_DEPTH)
                    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
mhp->npages is 0-10.

   157                  return -EINVAL;
   158          *wr_cnt = 1;
   159          wqe->fastreg.stag = cpu_to_be32(wr->key);
   160          wqe->fastreg.len = cpu_to_be32(mhp->ibmr.length);
   161          wqe->fastreg.va_base_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
   162          wqe->fastreg.va_base_lo_fbo =
   163                                  cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
   164          wqe->fastreg.page_type_perms = cpu_to_be32(
   165                  V_FR_PAGE_COUNT(mhp->npages) |
   166                  V_FR_PAGE_SIZE(ilog2(wr->mr->page_size) - 12) |
   167                  V_FR_TYPE(TPT_VATO) |
   168                  V_FR_PERMS(iwch_ib_to_tpt_access(wr->access)));
   169          p = &wqe->fastreg.pbl_addrs[0];
   170          for (i = 0; i < mhp->npages; i++, p++) {
                            ^^^^^^^^^^^^^^^
That implied i is 0-9.

   171  
   172                  /* If we need a 2nd WR, then set it up */
   173                  if (i == T3_MAX_FASTREG_FRAG) {
                            ^^^^^^^^^^^^^^^^^^^^^^^^
T3_MAX_FASTREG_FRAG is 10 so this condition can't be true.

   174                          *wr_cnt = 2;
   175                          wqe = (union t3_wr *)(wq->queue +
   176                                  Q_PTR2IDX((wq->wptr+1), wq->size_log2));
   177                          build_fw_riwrh((void *)wqe, T3_WR_FASTREG, 0,
   178                                 Q_GENBIT(wq->wptr + 1, wq->size_log2),
   179                                 0, 1 + mhp->npages - T3_MAX_FASTREG_FRAG,
   180                                 T3_EOP);
   181  
   182                          p = &wqe->pbl_frag.pbl_addrs[0];
   183                  }
   184                  *p = cpu_to_be64((u64)mhp->pages[i]);
   185          }
   186          *flit_cnt = 5 + mhp->npages;
   187          if (*flit_cnt > 15)
   188                  *flit_cnt = 15;
   189          return 0;
   190  }

regards,
dan carpenter
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