Hi, On 10/18/2017 10:12 AM, Christoph Hellwig wrote: > On Tue, Oct 17, 2017 at 06:18:55PM +0300, Leon Romanovsky wrote: >> There are PCIe root complex that are able to optimize their >> performance when incoming data is multiple full cache lines. >> >> Expose the device capability to pad the ending of incoming packets >> (scatter) to full cache line such that the last upstream write >> generated by the incoming packet will be a full cache line. > Any why would this be a user controller option? Isn't this something > that the kernel should set up automatically instead of needing arcane > tribal knowledge in the ULPs and applications? User should consider several factors before activating this feature: - In case of high CPU memory load (which may cause PCI backpressure in turn), if a large percent of the writes are partial cache line, this feature should be checked as an optional solution. - This feature might reduce performance if most packets are between one and two cache lines and PCIe throughput has reached its maximum capacity. E.g. 65B packet from the network port will lead to 128B write on PCIe, which may cause trafiic on PCIe to reach high throughput. Userspace series will follow. Thanks, Noa -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
