On Tue, Oct 17, 2017 at 06:18:55PM +0300, Leon Romanovsky wrote: > There are PCIe root complex that are able to optimize their > performance when incoming data is multiple full cache lines. > > Expose the device capability to pad the ending of incoming packets > (scatter) to full cache line such that the last upstream write > generated by the incoming packet will be a full cache line. Any why would this be a user controller option? Isn't this something that the kernel should set up automatically instead of needing arcane tribal knowledge in the ULPs and applications? -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
