On Wed, Mar 06, 2024 at 11:14:00PM +0100, Christoph Hellwig wrote:
> On Wed, Mar 06, 2024 at 01:44:56PM -0400, Jason Gunthorpe wrote:
> > There is a list of interesting cases this has to cover:
> >
> > 1. Direct map. No dma_addr_t at unmap, multiple HW SGLs
> > 2. IOMMU aligned map, no P2P. Only IOVA range at unmap, single HW SGLs
> > 3. IOMMU aligned map, P2P. Only IOVA range at unmap, multiple HW SGLs
> > 4. swiotlb single range. Only IOVA range at unmap, single HW SGL
> > 5. swiotlb multi-range. All dma_addr_t's at unmap, multiple HW SGLs.
> > 6. Unaligned IOMMU. Only IOVA range at unmap, multiple HW SGLs
> >
> > I think we agree that 1 and 2 should be optimized highly as they are
> > the common case. That mainly means no dma_addr_t storage in either
>
> I don't think you can do without dma_addr_t storage. In most cases
> your can just store the dma_addr_t in the LE/BE encoded hardware
> SGL, so no extra storage should be needed though.
RDMA (and often DRM too) generally doesn't work like that, the driver
copies the page table into the device and then the only reason to have
a dma_addr_t storage is to pass that to the dma unmap API. Optionally
eliminating long term dma_addr_t storage would be a worthwhile memory
savings for large long lived user space memory registrations.
> > 3 is quite similar to 1, but it has the IOVA range at unmap.
>
> Can you explain what P2P case you mean? The switch one with the
> bus address is indeed basically the same, just with potentioally a
> different offset, while the through host bridge case is the same
> as a normal iommu map.
Yes, the bus address case. The IOMMU is turned on, ACS on a local
switch is off.
All pages go through the IOMMU in the normal way except P2P pages
between devices on the same switch. (ie the dma_addr_t is CPU physical
of the P2P plus an offset). RDMA must support a mixture of IOVA and
P2P addresses in the same IO operation.
I suppose it would make more sense to say it is similar to 6.
> > 5 is the slowest and has the most overhead.
>
> and 5 could be broken into multiple 4s at least for now. Or do you
> have a different dfinition of range here?
I wrote the list as from a single IO operation perspective, so all but
5 need to store a single IOVA range that could be stored in some
simple non-dynamic memory along with whatever HW SGLs/etc are needed.
The point of 5 being different is because the driver has to provide a
dynamically sized list of dma_addr_t's as storage until unmap. 5 is
the only case that requires that full list.
So yes, 5 could be broken up into multiple IOs, but then the
specialness of 5 is the driver must keep track of multiple IOs..
> > So are you thinking something more like a driver flow of:
> >
> > .. extent IO and get # aligned pages and know if there is P2P ..
> > dma_init_io(state, num_pages, p2p_flag)
> > if (dma_io_single_range(state)) {
> > // #2, #4
> > for each io()
> > dma_link_aligned_pages(state, io range)
> > hw_sgl = (state->iova, state->len)
> > } else {
>
> I think what you have a dma_io_single_range should become before
> the dma_init_io. If we know we can't coalesce it really just is a
> dma_map_{single,page,bvec} loop, no need for any extra state.
I imagine dma_io_single_range() to just check a flag in state.
I still want to call dma_init_io() for the non-coalescing cases
because all the flows, regardless of composition, should be about as
fast as dma_map_sg is today.
That means we need to always pre-allocate the IOVA in any case where
the IOMMU might be active - even on a non-coalescing flow.
IOW, dma_init_io() always pre-allocates IOVA if the iommu is going to
be used and we can't just call today's dma_map_page() in a loop on the
non-coalescing side and pay the overhead of Nx IOVA allocations.
In large part this is for RDMA, were a single P2P page in a large
multi-gigabyte user memory registration shouldn't drastically harm the
registration performance by falling down to doing dma_map_page, and an
IOVA allocation, on a 4k page by page basis.
The other thing that got hand waved here is how does dma_init_io()
know which of the 6 states we are looking at? I imagine we probably
want to do something like:
struct dma_io_summarize summary = {};
for each io()
dma_io_summarize_range(&summary, io range)
dma_init_io(dev, &state, &summary);
if (state->single_range) {
} else {
}
dma_io_done_mapping(&state); <-- flush IOTLB once
At least this way the DMA API still has some decent opportunity for
abstraction and future growth using state to pass bits of information
between the API family.
There is some swiotlb complexity that needs something like this, a
system with iommu can still fail to coalesce if the pages are
encrypted and the device doesn't support DMA from encrypted pages. We
need to check for P2P pages, encrypted memory pages, and who knows
what else.
> And we're back to roughly the proposal I sent out years ago.
Well, all of this is roughly your original proposal, just with
different optimization choices and some enhancement to also cover
hmm_range_fault() users.
Enhancing the single sgl case is not a big change, I think. It does
seem simplifying for the driver to not have to coalesce SGLs to detect
the single-SGL fast-path.
> > This is not quite what you said, we split the driver flow based on
> > needing 1 HW SGL vs need many HW SGL.
>
> That's at least what I intended to say, and I'm a little curious as what
> it came across.
Ok, I was reading the discussion more about as alignment than single
HW SGL, I think you ment alignment as implying coalescing behavior
implying single HW SGL..
Jason
