On Fri, Aug 13, 2021 at 05:25:49PM -0500, Tatyana Nikolova wrote: > >> 1. Software writing the valid bit in the WQE. > >> 2. Software reading shadow memory (hw_tail) value. > > > You are missing an ordered atomic on this read it looks like > > Hi Jason, > > Why do you think we need atomic ops in this case? We aren't trying > to protect from multiple threads but CPU re-ordering of a write and > a read. Which is what the atomics will do. Barriers are only appropriate when you can't add atomic markers to the actual data that needs ordering. Jason
