From: Chuck Lever III > Sent: 09 June 2021 15:37 > > Hi David- > > > On Jun 9, 2021, at 10:10 AM, David Laight <David.Laight@xxxxxxxxxx> wrote: > > > > And I still don't know what a ULP is. > > Upper Layer Protocol. > > That's a generic term for an RDMA verbs consumer, like NVMe or > RPC-over-RDMA. No wonder I don't spot what it meant. I'm guessing you have something specific in mind for RDMA as well. Don't assume that everyone has read all the high level protocol specs (and remembers the all the TLA (and ETLA)) when talking about very low level hardware features. Especially when you are also referring to how the 'relaxed ordering' bit of a PCIe write TLP is processed. This all makes your commit message even less meaningful. In principle some writel() could generate PCIe write TLP (going to the target) that have the 'relaxed ordering' bit set. So a ULP that supports relaxed ordering could actually expect to generate them - even though there is probably no method of setting the bit. Although, in principle, I guess that areas that are 'prefetchable' (for reads) could be deemed suitable for relaxed writes. (That way probably lies madness and a load of impossible to fix timing bugs!) David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
